1. Field of the Invention
The present invention relates to a circuit of generating a data strobe DQS signal in a semiconductor memory device and a method of generating the same, and more particularly to, a circuit of generating a DQS signal and a method of generating the same capable of generating a DQS signal with one clock of preamble time at any time, regardless of process, voltage, temperature PVT, and operation frequency, by identifying paths of both a DQS preamble signal and a DQS output control signal.
2. Discussion of Related Art
In general, a synchronous semiconductor memory device such as a double data rate DDR SDRAM transfers data to a chip-set according to a DQS signal. Therefore, a timing of the DQS signal is very important.
FIG. 1 is a circuit diagram illustrating a circuit of generating a DQS signal in a semiconductor memory device of the conventional art, which will be described about the operation thereof with reference to FIG. 2.
Referring to FIG. 2, a DQS signal generation circuit in a semiconductor memory device of the conventional art is comprised of a DQS pre-signal generation unit 10, a DQS data generation unit 20, a DQS output control signal generation unit 30, and a DQS signal driver 40.
The DQS pre-signal generation unit 10 generates a signal for assuring a preamble time (tRPRE in FIG. 2) of the DQS. The DQS data generation unit 20 generates a DQS data. The DQS output control signal generation unit 30 generates a signal for transferring the DQS data to a DQS pad 50. The DQS driver 40 drives the DQS signal to have a constant level.
With reference to the DQS pre-signal generation unit 10, after inputting a read command, a high state preamble control signal qsen_pre is generated, as shown in FIG. 2, before one clock of CAS latency.
In case that the CAS latency doesn't include a decimal point, that is, the CAS latency is a constant such as 2, 3, 4, clx5 is a low state, which leads a transmission gate T2 to be turned on. In response to this, an internal rising clock rclk_dll is inverted by a NAND gate G1. An output of the NAND gate G1 is delayed in a delay unit comprised of inverters I1 to I5 after passing through a NOR gate G2. An output of the delay unit is inverted and then becomes a DQS pre-signal qspre_clk in a low state, as shown in FIG. 2.
In case that the CAS latency includes a decimal point, that is, the CAS latency is like 1.5, 2.5, clx5 is a high state, which leads the transmission gate T1 to be turned on. In response to this, an internal falling clock fclk_dll is inverted by the NAND gate G1. The output of the NAND gate G1 is delayed in the delay unit comprised of inverters I1 to I5 after passing through the NOR gate G2. The output of the delay unit is inverted and then becomes the DQS pre-signal qspre_clk in a low state, as shown in FIG. 2.
A delay value of the delay unit is decided by switches sw1 to sw4, and the DQS pre-signal generation unit 10 is enabled or disabled according to an option signal opt.
The DQS data generation unit 20 generates a DQS data toggling to a high or a low state. For instance, when the CAS latency includes a decimal point, clx5 becomes a low state, which leads transmission gates T3, T5 to be turned on. In response to this, an output rdo receives a high data, while another output fdo receives a low data.
For instance, when the CAS latency doesn't include a decimal point, clx5 become a low state, which leads the transmission gates T3, T5 to be turned on. As a result of this, the output rdo receives a high data, while the output fdo receives a low data.
The DQS output control signal generation unit 30 generates a control signal for driving the DQS data out after the CAS latency.
A NAND gate G3 combines a rising data enable signal routen and an internal rising clock rclk_dll, and then the output of the NAND gate G3 is inverted therein by an inverter. As a result, a first control signal rclk_do is generated. A NAND gate G4 combines a falling data enable signal fouten and an internal falling clock fclk_dll and then the output of the NAND gate G4 is inverted therein by an inverter. As a result, a second control signal fclk_do is generated.
The first control signal rclk_do is a control signal to drive a rising data of the DQS data out, while the second control signal fclk_do is a control signal to drive a falling data of the DQS data out.
The DQS driver 40 is comprised of a first driver 40A and a second driver 40B.
A PMOS transistor Q1 is turned on according to the output qspre_clk of the DQS pre-signal generation unit 10, and thus stored a high data in a latch 60. A NMOS transistor Q2 is turned on according to a signal inverted by an inverter 18, and thus the DQS is driven from a high impedance state to a low state.
The DQS data generated from the DQS data generation unit 20 is outputted to the DQS pad 50 by turns for a high state and a low state according to the control signals from the DQS output control signal generation unit 30, which will be explained in detail as follows.
The first driver 40A and the second driver 40B have a similar configuration except the scheme of the PMOS transistor Q1 in the second driver 40B. Therefore, there will not be another explanation of the same section.
For reference, a control signal qsen is to turn on or off the DQS driver. Moreover, an option signal opt is to select a DQS buffer in case of including a plurality of DQS buffers. That is, in a semiconductor memory device comprised of x4/x8/x16, it is divided into an upper DQS and a lower DQS. During this, the two of the DQS are all operated in x16, while the upper DQS is only operated in x4/x8.
For instance, in case that the output rdo of the DQS data generator is a high state and the output fdo, as shown in FIG. 2, is a low state, when the first control signal rclk_do of the DQS control signal generation unit 30 in risen to a high state, an output of a NAND gate G5 becomes a low state. Therefore, transistors Q4, Q5 are turned on, and thus a node K2 becomes a high state. As an output of a latch 70 is a low state, a PMOS transistor Q6 is turned on but a NMOS transistor Q2 is turned off. Accordingly, the DQS is risen to a high level.
Then, as shown in FIG. 2, when the second control signal fclk_do of the DQS control signal generation unit 30 is risen to a high state, an output of a NAND gate G6 becomes a low state. Accordingly, NMOS transistors Q7, Q8 are turned on, and thus the node K2 becomes a ground potential. As the node K2 is the ground potential, the output of the latch 70 becomes a high state.
The PMOS transistor Q6 is turned off, while the NMOS transistor Q2 is turned off. As a result, the DQS is fallen down from a high state to a low state.
Repeating these operations, the DQS signal is generated, as shown in FIG. 2.
As aforementioned, in the conventional art, the DQS preamble signal is transited from a high impedance state to a low state by a preamble signal path (A in FIG. 1).
On the other hand, the DQS data is transited from a low state to a high state by a DQS output control signal path (B in FIG. 1).
That is, there are two different paths for the DQS outputted according to the output qspre_clk of the DQS pre-signal generation unit 10 and the DQS outputted according to outputs rclk_do, fclk_do of the DQS control signal generation unit 30, and preamble time tRPRE of the two DQS is deviated, because the delay values by PVT of the two paths are different.